1. Field of the Invention
The present invention relates to sense amplifiers, and in particular, to single-ended complementary metal oxide semiconductor field effect transistor ("MOSFET") sense amplifiers.
2. Description of the Related Art Referring to FIG. 1, a conventional sense amplifier circuit design is illustrated in which N-type MOSFETs ("N-MOSFETs") are used. Enhancement mode N-MOS FETs Q1.1-Q1.4, Q1.6-Q1.8, Q1.10, Q1.12 and depletion mode N-MOSFETs Q1.5, Q1.9, Q1.11 are interconnected in five stages as shown. The MOSFET geometries, e.g. the channel widths and lengths, are as shown below in Table 1.1.
TABLE 1.1 ______________________________________ (PRIOR ART) CHANNEL WIDTH CHANNEL LENGTH MOSFET (MICRONS) (MICRONS) ______________________________________ Q1.1 17.8 2 Q1.2 6.5 2.7 Q1.3 22 2.5 Q1.4 10 2 Q1.5 7 5.3 Q1.6 40 2.5 Q1.7 27 2.5 Q1.8 33 2.5 Q1.9 7 7 Q1.10 10 2.5 Q1.11 10 3.5 Q1.12 30 2.0 ______________________________________
The circuit of FIG. 1 is biased between power supplies VDD and VSS, where the positive supply VDD is typically set equal to a nominal VCC value of five volts, and the negative supply VSS is typically set at circuit reference, or ground GND. A programming, or enablement, control input PZ drives the gates of Q1.1 and Q1.4. This input PZ is typically set at a logical high value (approximately equal to VCC) when the circuit is in a read mode. The input signal V1.1 is the input voltage signal received from a bit line of a memory cell (not shown).
The input voltage V1.1 has two values, a logical 1 in the erase mode, and a logical 0 in the program mode, and is applied to the gates of Q1.3, Q1.6 and Q1.8, as shown. This produces an amplified corresponding signal voltage V1.2 of opposite polarity, or signal phase, which is applied to the gates of Q1.2, Q1.5 and Q1.7, as shown. An amplified and inverted (with respect to the input voltage V1.1) signal voltage V1.3 is produced, which is applied to the gate of Q1.10. (This voltage V1.3 has a voltage level which is lower than voltage V1.2 by the threshold voltage of Q1.7.) The resulting signal, a further amplified and inverted signal voltage V1.4, is applied to the gate of Q1.12 to finally produce the output signal voltage V1.5, which is the digital output signal having logic voltage levels approximately equal to zero and VCC volts. Typical voltage values for these voltages V1.1-V1.5, as well as the typical supply current I.sub.s1 for this circuit, are shown below in Table 1.2, for the VCC and temperature indicated.
TABLE 1.2 ______________________________________ (PRIOR ART) I.sub.S1 INPUT V1.1 V1.2 V1.3 V1.4 V1.5 (micro- STATE (volts) (volts) (volts) (volts) (volts) amperes) ______________________________________ ERASE 1.098 2.523 1.372 2.462 0.21 1220 ("1") PRO- 1.085 2.822 1.658 0.361 4.96 728 GRAM ("0") ______________________________________ Test Conditions: VCC = 5.0 Volts Temperature = 27.degree. C.
The single-ended N-MOSFET sense amplifier of FIG. 1, with the MOSFET geometries as listed above in Table 1.1 and signal voltage levels as listed above in Table 1.2, provides reasonably good switching speed, i.e. reasonably low input-to-output signal propagation delay. Exemplary transition delay times from input pin to output pin (i.e. for a full IC simulation including additional circuitry external to the circuit of FIG. 1) under various VCC and ambient temperature conditions are shown below in Table 1.3
TABLE 1.3 ______________________________________ (PRIOR ART) DELAY TIME TRANSITION (full IC) INPUT OUTPUT (nanoseconds) CONDITIONS ______________________________________ L.fwdarw.H H.fwdarw.L 7.1 VCC = 4.75 volts H.fwdarw.L L.fwdarw.H 6.8 Temp. = 55.degree. C. L.fwdarw.H H.fwdarw.L 7.5 VCC = 4.75 volts H.fwdarw.L L.fwdarw.H 7.4 Temp. = 85.degree. C. L.fwdarw.H H.fwdarw.L 6.4 VCC = 5.25 volts H.fwdarw.L L.fwdarw.H 5.4 Temp. = 0.degree. C. ______________________________________ Where: H = logical one ("1") L = logical zero ("0")
Accordingly, typical sense amplifiers currently available generally offer performance characteristics and speed sufficient for today's programmable logic devices. However, a number of problems still exist, particularly for single-ended complementary MOSFET sense amplifiers.
One problem involves variations in trip current for the sense amplifier. Trip current tends to vary across a semiconductor wafer by approximately .+-.15 micro-amperes. This variation is a function of the depletion current dose and the effective channel length of the MOSFETs integrated onto the wafer. Such trip current variation is particularly evident when depletion mode MOSFETs are used, such as depletion mode N-MOSFETs.
A second problem involves the voltage swing required on the bit line to trip the sense amplifier. This voltage swing can often be as low as five millivolts, which results in a very low noise margin for the sense amplifier.
Still another problem encountered in many sense amplifier designs is oscillation or instability due to "ground bounce" effects. This often occurs when some of the output signal (e.g. from devices downstream in the signal path) feeds back into one or more of the input or intermediate stages of the sense amplifier by way of shared ground paths. While this can often be a function of circuit layout, it is also a function of static voltage levels and threshold voltage levels among the various stages of the sense amplifier.